1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more specifically to a ultra-violet erasable electrically programmable read only memory in which each elementary bit or each memory cell is composed of two-transistors assigned to a reading transistor and a writing transistor, respectively.
2. Description of Related Art
In the prior art, it has been said that this type of non-volatile semiconductor memory is not generally suitable to a large capacity ROM (read only memory), since each elementary bit or each memory cell is composed of two transistors. However, a transistor exclusively used for reading can be configured to have a decreased threshold voltage and an enlarged channel width, so that a so-called ON current will be large. Therefore, a reading can be executed at a high speed. On the other hand, a transistor exclusively used for writing can be configured to have a substrate impurity concentration for maximizing a writing efficiency, without paying consideration to the ON current at the reading time. Therefore, a writing speed can be elevated.
Conventionally, one EPROM (ultra-violet erasable electrically programmable read only memory) of the two-transistor type has been proposed by J. Pathak et al "A 50 MHz CMOS Programmable Logic Device", ISSCC '88, THAM 11.4, pp 144-145. This conventional EPROM cell is configured to realize a high speed reading. However, it sacrifices a cell area, namely, an integration density. In brief, the conventional EPROM cell is such that a floating gate of a writing transistor and a floating gate of a reading transistor are formed of the same layer at the same level. In addition, a drain of the reading transistor is connected to the substrate itself. This means that a plurality of reading transistors are connected in parallel to a corresponding reading digit line.
In this conventional EPROM cell of the two-transistor type, it is considered from a conventional writing method for EPROMs that a writing voltage is applied between a control gate and a source of the writing transistor while applying a certain voltage between the source and a drain of the writing transistor, so as to turn on a channel of the same writing transistor. In this connection, in order to permit to write a arbitrary bit or memory cell, the transistors of each memory cell are connected in parallel to a digit line (called "parallel arrangement" hereinafter), not in series to a digit line (called "series arrangement" hereinafter). It should be noted that all conventional ROMs including one-transistor type ROMs have been of the "parallel arrangement". In the two-transistor type EPROM, however, the above mentioned demand permitting to write a arbitrary bit or memory cell is directed to the writing transistor, but it is not inevitably required for the reading transistor.
As will be seen from the above, the conventional two-transistor type EPROM has been disadvantageous in that it requires a large cell ares, since not only the writing transistors but also the reading transistors are located in the "parallel arrangement", in addition to the fact that an enlarged cell area is required because one transistor is replaced with two transistors.